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Designing Estimator/Predictor Digital Phase-Locked LoopsSignal delays in equipment compensated automatically. New approach to design of digital phase-locked loop (DPLL) incorporates concepts from estimation theory and involves decomposition of closed-loop transfer function into estimator and predictor. Estimator provides recursive estimates of phase, frequency, and higher order derivatives of phase with respect to time, while predictor compensates for delay, called "transport lag," caused by PLL equipment and by DPLL computations.
Document ID
19880000333
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Statman, J. I.
(Caltech)
Hurd, W. J.
(Caltech)
Date Acquired
August 13, 2013
Publication Date
June 1, 1988
Publication Information
Publication: NASA Tech Briefs
Volume: 12
Issue: 6
ISSN: 0145-319X
Subject Category
Electronic Systems
Report/Patent Number
NPO-17196
Accession Number
88B10333
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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