Digital carrier demodulation for the DSN Advanced Receiver

The digital in-phase and quadrature (I and Q) carrier demodulation for the Deep Space Network's (DSN) Advanced Receiver is described and analyzed. The system provides coherent demodulation for a variety of modulation formats including Binary Phase Shift Keying (BPSK), BPSK with a carrier residual, Quadrature Phase Shift Keying (QPSK), Offset-QPSK (OQPSK), and Minimum Shift Keying (MSK). The focus is on the theory and hardware design of the halfband filters which are the integral part of the demodulator. The underlying theory of the filters is summarized, a breadboard hardware design is described, and a VLSI implementation is proposed which significantly decreases the hardware. A second important problem analyzed is DC-offset in the demodulator. This is a serious problem which translates into bias error in the residual carrier phase detector. The dynamic range of the complex mixer is analyzed using a probabilistic approach. It is deduced that the resulting static phase error is less than 0.2 deg when the ratio of carrier power to noise power in the demodulator input bandwidth is -72 dB or higher. Thus, the static phase error is negligible at a carrier power to noise spectral density of 0 dB-Hz for a 15 MHz bandwidth demodulator.