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Fault-Tolerant Clock Synchronization Validation MethodologyA validation method for the synchronization subsystem of a fault-tolerant computer system is presented. The high reliability requirement of flight-crucial systems precludes the use of most traditional validation methods. The method presented utilizes formal design proof to uncover design and coding errors and experimentation to validate the assumptions of the design proof. The experimental method is described and illustrated by validating the clock synchronization system of the Software Implemented Fault Tolerance computer. The design proof of the algorithm includes a theorem that defines the maximum skew between any two nonfaulty clocks in the system in terms of specific system parameters. Most of these parameters are deterministic. One crucial parameter is the upper bound on the clock read error, which is stochastic. The probability that this upper bound is exceeded is calculated from data obtained by the measurement of system parameters. This probability is then included in a detailed reliability analysis of the system.
Document ID
19880035377
Document Type
Reprint (Version printed in journal)
Authors
Ricky W Butler (Langley Research Center Hampton, Virginia, United States)
Daniel L Palumbo (Langley Research Center Hampton, Virginia, United States)
Sally C Johnson (Langley Research Center Hampton, Virginia, United States)
Date Acquired
August 13, 2013
Publication Date
November 1, 1987
Publication Information
Publication: Journal of Guidance, Control, and Dynamics
Volume: 10
Issue: 6
ISSN: 0731-5090
Subject Category
Computer Systems
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Keywords
Computer systems
Operating systems
Regression analysis
Fault tolerance
Flight control system
NASA Langley Research Center
Interprocessor communication
Mathematical analysis
Data structures