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A neurocomputer based on an analog-digital hybrid architectureA novel analog-digital hybrid architecture based on the utilization of high density digital random access memories for the storage of the synaptic weights of a neural network, and high speed analog hardware to perform neural computation is described. An electronic neurocomputer based on such an architecture is ideally suited for investigating the dynamics, associative recall properties, and computational capabilities of neural networks and provides significant speed improvement in comparison to conventional software based neural network simulations. As a demonstration of the feasibility of the hybrid architectural concept, a prototype breadboard hybrid neurocomputer system with 32 neurons has been designed and fabricated with off-the-shelf hardware components. The performance of the breadboard system has been tested for variety of applications including associative memory and combinatorial problem solving such as Graph Coloring, and is discussed in this paper.
Document ID
19880045607
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Moopenn, A.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Thakoor, A. P.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Duong, T.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Khanna, S. K.
(California Institute of Technology Jet Propulsion Laboratory, Pasadena, United States)
Date Acquired
August 13, 2013
Publication Date
January 1, 1987
Subject Category
Computer Operations And Hardware
Meeting Information
Meeting: IEEE Annual International Conference on Neural Networks
Location: San Diego, CA
Country: United States
Start Date: June 21, 1987
End Date: June 24, 1987
Accession Number
88A32834
Distribution Limits
Public
Copyright
Other

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