The economic payoff for a state-of-the-art high-efficiency flat-plate crystalline silicon solar cell technologyIn 1986 during the flat-plate solar array project, silicon solar cells 4.0 sq cm in area were fabricated at the Jet Propulsion Laboratory (JPL) with a conversion efficiency of 20.1 percent (AM1.5-global). Sixteen cells were processed with efficiencies measuring 19.5 percent (AM1.5 global) or better. These cells were produced using refined versions of conventional processing methods, aside from certain advanced techniques that bring about a significant reduction in a major mechanism (surface recombination) that limits cell efficiency. Wacker Siltronic p-type float-zone 0.18-ohm-cm wafers were used. Conversion efficiencies in this range have previously been reported by other researchers, but generally on much smaller (0.5 vs. 4.0 cm) devices which have undergone sophisticated and costly processing steps. An economic analysis is presented of the potential payoffs for this approach, using the Solar Array Manufacturing Industry Costing Standards (SAMICS) methodology. The process sequence used and the assumptions made for capturing the economies of scale are presented.
Document ID
19880047208
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Bickler, Donald B. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Callaghan, W. T. (California Institute of Technology Jet Propulsion Laboratory, Pasadena, United States)