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Programmable synaptic chip for electronic neural networksA binary synaptic matrix chip has been developed for electronic neural networks. The matrix chip contains a programmable 32X32 array of 'long channel' NMOSFET binary connection elements implemented in a 3-micron bulk CMOS process. Since the neurons are kept off-chip, the synaptic chip serves as a 'cascadable' building block for a multi-chip synaptic network as large as 512X512 in size. As an alternative to the programmable NMOSFET (long channel) connection elements, tailored thin film resistors are deposited, in series with FET switches, on some CMOS test chips, to obtain the weak synaptic connections. Although deposition and patterning of the resistors require additional processing steps, they promise substantial savings in silicon area. The performance of synaptic chip in a 32-neuron breadboard system in an associative memory test application is discussed.
Document ID
19890041672
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Moopenn, A.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Langenbacher, H.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Thakoor, A. P.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Khanna, S. K.
(California Institute of Technology Jet Propulsion Laboratory, Pasadena, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1988
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: IEEE Conference on Neural Information Processing Systems
Location: Denver, CO
Country: United States
Start Date: November 8, 1987
End Date: November 12, 1987
Accession Number
89A29043
Distribution Limits
Public
Copyright
Other

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