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Multiprocessor performance modeling with ADASA graph managing strategy referred to as the Algorithm to Architecture Mapping Model (ATAMM) appears useful for the time-optimized execution of application algorithm graphs in embedded multiprocessors and for the performance prediction of graph designs. This paper reports the modeling of ATAMM in the Architecture Design and Assessment System (ADAS) to make an independent verification of ATAMM's performance prediction capability and to provide a user framework for the evaluation of arbitrary algorithm graphs. Following an overview of ATAMM and its major functional rules are descriptions of the ADAS model of ATAMM, methods to enter an arbitrary graph into the model, and techniques to analyze the simulation results. The performance of a 7-node graph example is evaluated using the ADAS model and verifies the ATAMM concept by substantiating previously published performance results.
Document ID
Document Type
Conference Paper
Hayes, Paul J.
(NASA Langley Research Center Hampton, VA, United States)
Andrews, Asa M.
(Planning Research Corp. Hampton, VA, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1989
Subject Category
Computer Systems
Report/Patent Number
AIAA PAPER 89-3012
Meeting Information
AIAA Computers in Aerospace Conference(Monterey, CA)
Accession Number
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