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Floating point arithmetic in future supercomputersConsiderations in the floating-point design of a supercomputer are discussed. Particular attention is given to word size, hardware support for extended precision, format, and accuracy characteristics. These issues are discussed from the perspective of the Numerical Aerodynamic Simulation Systems Division at NASA Ames. The features believed to be most important for a future supercomputer floating-point design include: (1) a 64-bit IEEE floating-point format with 11 exponent bits, 52 mantissa bits, and one sign bit and (2) hardware support for reasonably fast double-precision arithmetic.
Document ID
19900025640
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
Authors
Bailey, David H.
(NASA Ames Research Center Moffett Field, CA, United States)
Barton, John T.
(NASA Ames Research Center Moffett Field, CA, United States)
Simon, Horst D.
(Boeing Computer Services Seattle, WA, United States)
Fouts, Martin J.
(Intergraph Corp. Palo Alto, CA, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1989
Publication Information
Publication: International Journal of Supercomputer Applications
Volume: 3
ISSN: 0890-2720
Subject Category
Computer Programming And Software
Accession Number
90A12695
Distribution Limits
Public
Copyright
Other

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