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Record Details

Record 17 of 33
Floating point arithmetic in future supercomputers
Author and Affiliation:
Bailey, David H.(NASA Ames Research Center, Moffett Field, CA, United States)
Barton, John T.(NASA Ames Research Center, Moffett Field, CA, United States)
Simon, Horst D.(Boeing Computer Services, Seattle, WA, United States)
Fouts, Martin J.(Intergraph Corp., Palo Alto, CA, United States)
Abstract: Considerations in the floating-point design of a supercomputer are discussed. Particular attention is given to word size, hardware support for extended precision, format, and accuracy characteristics. These issues are discussed from the perspective of the Numerical Aerodynamic Simulation Systems Division at NASA Ames. The features believed to be most important for a future supercomputer floating-point design include: (1) a 64-bit IEEE floating-point format with 11 exponent bits, 52 mantissa bits, and one sign bit and (2) hardware support for reasonably fast double-precision arithmetic.
Publication Date: Jan 01, 1989
Document ID:
19900025640
(Acquired Nov 28, 1995)
Accession Number: 90A12695
Subject Category: COMPUTER PROGRAMMING AND SOFTWARE
Document Type: Journal Article
Publication Information: International Journal of Supercomputer Applications (ISSN 0890-2720); 3; 86-90
Publisher Information: United States
Financial Sponsor: NASA; United States
Organization Source: NASA Ames Research Center; Moffett Field, CA, United States
Boeing Computer Services Co.; Seattle, WA, United States
Intergraph Corp.; Palo Alto, CA, United States
Description: 5p; In English
Distribution Limits: Unclassified; Publicly available; Unlimited
Rights: Copyright
NASA Terms: COMPUTER SYSTEMS DESIGN; FLOATING POINT ARITHMETIC; SUPERCOMPUTERS; TECHNOLOGICAL FORECASTING; ACCURACY; CRAY COMPUTERS; HARDWARE
Imprint And Other Notes: International Journal of Supercomputer Applications (ISSN 0890-2720), vol. 3, Fall 1989, p. 86-90.
Availability Source: Other Sources
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