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A quasi-passive CMOS pipeline D/A converterA novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.
Document ID
19900036552
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Wang, Fong-Jim
(California Univ. Los Angeles, CA, United States)
Temes, Gabor C.
(California, University Los Angeles, United States)
Law, Simon
(Xerox Microelectronics Center El Segundo, CA, United States)
Date Acquired
August 14, 2013
Publication Date
December 1, 1989
Publication Information
Publication: IEEE Journal of Solid-State Circuits
Volume: 24
ISSN: 0018-9200
Subject Category
Electronics And Electrical Engineering
Accession Number
90A23607
Funding Number(s)
CONTRACT_GRANT: NCC2-374
Distribution Limits
Public
Copyright
Other

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