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Record 1 of 559
A quasi-passive CMOS pipeline D/A converter
External Online Source: doi:10.1109/4.45017
Author and Affiliation:
Wang, Fong-Jim(California Univ., Los Angeles, CA, United States)
Temes, Gabor C.(California, University, Los Angeles, United States)
Law, Simon(Xerox Microelectronics Center, El Segundo, CA, United States)
Abstract: A novel pipeline digital-to-analog converter configuration, based on switched-capacitor techniques, is described. An n-bit D/A conversion can be implemented by cascading n + 1 unit cells. The device count of the circuit increases linearly, not exponentially, with the conversion accuracy. The new configuration can be pipelined. Hence, the conversion rate can be increased without requiring a higher clock rate. An experimental 10-bit DAC prototype has been fabricated using a 3-micron CMOS process. The results show that high-speed, high-accuracy, and low-power operation can be achieved without special process or postprocess trimming.
Publication Date: Dec 01, 1989
Document ID:
19900036552
(Acquired Nov 28, 1995)
Accession Number: 90A23607
Subject Category: ELECTRONICS AND ELECTRICAL ENGINEERING
Document Type: Journal Article
Publication Information: IEEE Journal of Solid-State Circuits (ISSN 0018-9200); 24; 1752-175
Publisher Information: United States
Contract/Grant/Task Num: NCC2-374
Financial Sponsor: NASA; United States
Organization Source: California Univ.; Los Angeles, CA, United States
Xerox Corp.; El Segundo, CA, United States
Description: 4p; In English
Distribution Limits: Unclassified; Publicly available; Unlimited
Rights: Copyright
NASA Terms: ANALOG TO DIGITAL CONVERTERS; CMOS; PIPELINING (COMPUTERS); ACCURACY; CAPACITORS; SWITCHING CIRCUITS
Imprint And Other Notes: IEEE Journal of Solid-State Circuits (ISSN 0018-9200), vol. 24, Dec. 1989, p. 1752-1755. Research supported by the Xerox Corp.
Miscellaneous Notes: Research supported by the Xerox Corp
Availability Source: Other Sources
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