A parallel row-based algorithm for standard cell placement with integrated error controlA new row-based parallel algorithm for standard-cell placement targeted for execution on a hypercube multiprocessor is presented. Key features of this implementation include a dynamic simulated-annealing schedule, row-partitioning of the VLSI chip image, and two novel approaches to control error in parallel cell-placement algorithms: (1) Heuristic Cell-Coloring; (2) Adaptive Sequence Length Control.
Document ID
19900041033
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Sargent, Jeff S. (Illinois Univ. Urbana, IL, United States)
Banerjee, Prith (Illinois, University Urbana, United States)