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a general model for memory interference in a multiprocessor system with memory hierarchyThe problem of memory interference in a multiprocessor system with a hierarchy of shared buses and memories is addressed. The behavior of the processors is represented by a sequence of memory requests with each followed by a determined amount of processing time. A statistical queuing network model for determining the extent of memory interference in multiprocessor systems with clusters of memory hierarchies is presented. The performance of the system is measured by the expected number of busy memory clusters. The results of the analytic model are compared with simulation results, and the correlation between them is found to be very high.
Document ID
19900050427
Document Type
Conference Paper
Authors
Taha, Badie A.
(Toledo Univ. OH, United States)
Standley, Hilda M.
(Toledo, University OH, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1989
Subject Category
COMPUTER SYSTEMS
Meeting Information
1989 International Conference on Parallel Processing(University Park, PA)
Funding Number(s)
CONTRACT_GRANT: NAG3-699
Distribution Limits
Public
Copyright
Other