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compiler-directed cache management in multiprocessorsThe necessity of finding alternatives to hardware-based cache coherence strategies for large-scale multiprocessor systems is discussed. Three different software-based strategies sharing the same goals and general approach are presented. They consist of a simple invalidation approach, a fast selective invalidation scheme, and a version control scheme. The strategies are suitable for shared-memory multiprocessor systems with interconnection networks and a large number of processors. Results of trace-driven simulations conducted on numerical benchmark routines to compare the performance of the three schemes are presented.
Document ID
19900060375
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Cheong, Hoichi
(Illinois Univ. Urbana, IL, United States)
Veidenbaum, Alexander V.
(Illinois, University Urbana, United States)
Date Acquired
August 14, 2013
Publication Date
June 1, 1990
Publication Information
Publication: Computer
Volume: 23
ISSN: 0018-9162
Subject Category
COMPUTER SYSTEMS
Funding Number(s)
CONTRACT_GRANT: NCC2-559
CONTRACT_GRANT: NSF MIP-84-10110
CONTRACT_GRANT: DE-FG02-85ER-25001
Distribution Limits
Public
Copyright
Other