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Addressable-Matrix Integrated-Circuit Test StructureMethod of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.
Document ID
19910000572
Document Type
Other - NASA Tech Brief
Authors
Sayah, Hoshyar R. (Caltech)
Buehler, Martin G. (Caltech)
Date Acquired
August 14, 2013
Publication Date
November 1, 1991
Publication Information
Publication: NASA Tech Briefs
Volume: 15
Issue: 11
ISSN: 0145-319X
Subject Category
ELECTRONIC COMPONENTS AND CIRCUITS
Report/Patent Number
NPO-18162
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.