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Digital Phase-Locked Loop With Phase And Frequency FeedbackAdvanced design for digital phase-lock loop (DPLL) allows loop gains higher than those used in other designs. Divided into two major components: counterrotation processor and tracking processor. Notable features include use of both phase and rate-of-change-of-phase feedback instead of frequency feedback alone, normalized sine phase extractor, improved method for extracting measured phase, and improved method for "compressing" output rate.
Document ID
19910000574
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Thomas, J. Brooks
(Caltech)
Date Acquired
August 14, 2013
Publication Date
November 1, 1991
Publication Information
Publication: NASA Tech Briefs
Volume: 15
Issue: 11
ISSN: 0145-319X
Subject Category
Electronic Systems
Report/Patent Number
NPO-17722
Accession Number
91B10574
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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