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an area model for on-chip memories and its applicationAn area model suitable for comparing data buffers of different organizations and arbitrary sizes is described. The area model considers the supplied bandwidth of a memory cell and includes such buffer overhead as control logic, driver logic, and tag storage. The model gave less than 10 percent error when verified against real caches and register files. It is shown that, comparing caches and register files in terms of area for the same storage capacity, caches generally occupy more area per bit than register files for small caches because the overhead dominates the cache area at these sizes. For larger caches, the smaller storage cells in the cache provide a smaller total cache area per bit than the register set. Studying cache performance (traffic ratio) as a function of area, it is shown that, for small caches, direct-mapped caches perform significantly better than four-way set-associative caches and, for caches of medium areas, both direct-mapped and set-associative caches perform better than fully associative caches.
Document ID
19910044492
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Mulder, Johannes M.
(Delft University of Technology, Netherlands)
Quach, Nhon T.
(Technische Univ. Delft, Netherlands)
Flynn, Michael J.
(Stanford University CA, United States)
Date Acquired
August 14, 2013
Publication Date
February 1, 1991
Publication Information
Publication: IEEE Journal of Solid-State Circuits
Volume: 26
ISSN: 0018-9200
Subject Category
ELECTRONICS AND ELECTRICAL ENGINEERING
Funding Number(s)
CONTRACT_GRANT: NSF MIP-88-22961
CONTRACT_GRANT: NAGW-419
Distribution Limits
Public
Copyright
Other