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Custom CMOS Reed Solomon coder for the Hubble Space TelescopeA VLSI coder is presented that can function either as an encoder or decoder for Reed-Solomon codes. VLSI is one approach to implementing high-performance Reed-Solomon decoders. There are three VLSI technologies that could be used: gate arrays, standard cells, and full custom. The first two approaches are relatively easy to implement, but are limited in both performance and density. Full-custom VLSI is used to achieve both circuit density and speed, and allows control of the amount of interconnect. Speed, which is a function of capacitance, which is a function of interconnect, is an important parameter in high-performance VLSI. A single 8.2 mm x 8.4 mm, 200,000 transistor CMOS chip implementation of the Reed-Solomon code required by the Hubble Space Telescope is reported. The chip features a 10-MHz sustained byte rate independent of error pattern. The 1.6-micron CMOS integrated circuit has complete decoder and encoder functions and uses a single data/system clock. Block lengths up to 255 bytes and shortened codes are supported with no external buffering. Erasure corrections and random error corrections are supported with programmable correction of up to 10 symbol errors. Correction time is independent of error pattern and the number of errors in the incoming message.
Document ID
19910068444
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Whitaker, S.
(Idaho Univ. Moscow, ID, United States)
Cameron, K.
(Idaho Univ. Moscow, ID, United States)
Owsley, P.
(Idaho Univ. Moscow, ID, United States)
Maki, G.
(NASA Space Engineering Research Center for VLSI System Design; Idaho, University Moscow, United States)
Date Acquired
August 14, 2013
Publication Date
January 1, 1990
Subject Category
Communications And Radar
Accession Number
91A53067
Funding Number(s)
CONTRACT_GRANT: NAGW-1406
Distribution Limits
Public
Copyright
Other

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