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A bipolar population counter using wave pipelining to achieve 2.5 x normal clock frequencyWave pipelining is a technique for pipelining digital systems that can increase clock frequency in practical circuits without increasing the number of storage elements. In wave pipelining, multiple coherent waves of data are sent through a block of combinational logic by applying new inputs faster than the delay through the logic. The throughput of a 63-b CML population counter was increased from 97 to 250 MHz using wave pipelining. The internal circuit is flowthrough combinational logic. Novel CAD methods have balanced all input-to-output paths to about the same delay. This allows multiple data waves to propagate in sequence when the circuit is clocked faster than its propagation delay.
Document ID
19920057643
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Wong, Derek C.
(NASA Headquarters Washington, DC United States)
De Micheli, Giovanni
(NASA Headquarters Washington, DC United States)
Flynn, Michael J.
(Stanford University CA, United States)
Huston, Robert E.
(LTX Corp. Trillium Div., San Jose, CA, United States)
Date Acquired
August 15, 2013
Publication Date
May 1, 1992
Publication Information
Publication: IEEE Journal of Solid-State Circuits
Volume: 27
Issue: 5 Ma
ISSN: 0018-9200
Subject Category
Computer Operations And Hardware
Accession Number
92A40267
Funding Number(s)
CONTRACT_GRANT: NSF MIP-88-22961
CONTRACT_GRANT: NAGW-419
Distribution Limits
Public
Copyright
Other

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