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A VLSI design for a trace-back Viterbi decoderA systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods.
Document ID
19920057696
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Truong, T. K.
(JPL Pasadena, CA, United States)
Shih, Ming-Tang
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Reed, Irving S.
(Southern California, University Los Angeles, CA, United States)
Satorius, E. H.
(JPL Pasadena, CA, United States)
Date Acquired
August 15, 2013
Publication Date
March 1, 1992
Publication Information
Publication: IEEE Transactions on Communications
Volume: 40
Issue: 3, Ma
ISSN: 0090-6778
Subject Category
Communications And Radar
Accession Number
92A40320
Distribution Limits
Public
Copyright
Other

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