Modeling of planar varactor frequency multiplier devices with blocking barriers

Models for optimization of planar frequency triplers with symmetrical C-V curves are presented. Role and limitation of various blocking barriers (oxide, Mott, heterojunction) are discussed. Devices with undoped drift regions (BIN) have moderate efficiency but a broad range of power operation, whereas devices with doped drift regions (BNN) have high efficiency in a narrow power window. In particular, an upper power limit of the BNN is caused by electron velocity saturation. Implementations in SiO2/Si and AlAs/GaAs and means for increasing the power of BNN structures are considered.