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Logic flowgraph methodology - A tool for modeling embedded systemsThe logic flowgraph methodology (LFM), a method for modeling hardware in terms of its process parameters, has been extended to form an analytical tool for the analysis of integrated (hardware/software) embedded systems. In the software part of a given embedded system model, timing and the control flow among different software components are modeled by augmenting LFM with modified Petrinet structures. The objective of the use of such an augmented LFM model is to uncover possible errors and the potential for unanticipated software/hardware interactions. This is done by backtracking through the augmented LFM mode according to established procedures which allow the semiautomated construction of fault trees for any chosen state of the embedded system (top event). These fault trees, in turn, produce the possible combinations of lower-level states (events) that may lead to the top event.
Document ID
19920066644
Document Type
Conference Paper
Authors
Muthukumar, C. T. (NASA Goddard Space Flight Center Greenbelt, MD, United States)
Guarro, S. B. (NASA Goddard Space Flight Center Greenbelt, MD, United States)
Apostolakis, G. E. (California, University Los Angeles, United States)
Date Acquired
August 15, 2013
Publication Date
January 1, 1991
Subject Category
COMPUTER PROGRAMMING AND SOFTWARE
Meeting Information
IEEE/AIAA Digital Avionics Systems Conference(Los Angeles, CA)
Distribution Limits
Public
Copyright
Other