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Efficient instruction sequencing with Inline Target InsertionInline target insertion, a specific compiler and pipeline implementation method for delayed branches with squashing, is defined. The method is shown to offer two important features not discovered in previous studies. First, branches inserted into branch slots are correctly executed. Second, the execution returns correctly from interrupts or exceptions with only one program counter. These two features result in better performance and less software/hardware complexity than conventional delayed branching mechanisms.
Document ID
19930045614
Acquisition Source
Legacy CDMS
Document Type
Reprint (Version printed in journal)
External Source(s)
Authors
Hwu, Wen-Mei W.
(Illinois Univ. Urbana, United States)
Chang, Pohua P.
(Intel Corp. Hillsboro, OR, United States)
Date Acquired
August 16, 2013
Publication Date
December 1, 1992
Publication Information
Publication: IEEE Transactions on Computers
Volume: 41
Issue: 12
ISSN: 0018-9340
Subject Category
Computer Programming And Software
Accession Number
93A29611
Funding Number(s)
CONTRACT_GRANT: N00014-90-J-1270
CONTRACT_GRANT: NSF MIP-88-09478
CONTRACT_GRANT: NAG1-613
CONTRACT_GRANT: N00014-88-K-0656
Distribution Limits
Public
Copyright
Other

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