High density packaging and interconnect of massively parallel image processorsThis paper presents conceptual designs for high density packaging of parallel processing systems. The systems fall into two categories: global memory systems where many processors are packaged into a stack, and distributed memory systems where a single processor and many memory chips are packaged into a stack. Thermal behavior and performance are discussed.
Document ID
19930049161
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Carson, John C. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Indin, Ronald J. (Irvine Sensors Corp. Costa Mesa, CA, United States)
Date Acquired
August 16, 2013
Publication Date
January 1, 1991
Publication Information
Publication: In: Infrared sensors: Detectors, electronics, and signal processing; Proceedings of the Meeting, San Diego, CA, July 24-26, 1991 (A93-33153 12-35)
Publisher: Society of Photo-Optical Instrumentation Engineers