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Application of multirate digital filter banks to wideband all-digital phase-locked loops designA new class of architecture for all-digital phase-locked loops (DPLL's) is presented in this article. These architectures, referred to as parallel DPLL (PDPLL), employ multirate digital filter banks (DFB's) to track signals with a lower processing rate than the Nyquist rate, without reducing the input (Nyquist) bandwidth. The PDPLL basically trades complexity for hardware-processing speed by introducing parallel processing in the receiver. It is demonstrated here that the DPLL performance is identical to that of a PDPLL for both steady-state and transient behavior. A test signal with a time-varying Doppler characteristic is used to compare the performance of both the DPLL and the PDPLL.
Document ID
19930068871
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Sadr, Ramin
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Shah, Biren
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Hinedi, Sami
(JPL Pasadena, CA, United States)
Date Acquired
August 16, 2013
Publication Date
January 1, 1993
Publication Information
Publisher: Institute of Electrical and Electronics Engineers, Inc.
Subject Category
Electronics And Electrical Engineering
Accession Number
93A52868
Funding Number(s)
PROJECT: RTOP 310-30-70-92-01
Distribution Limits
Public
Copyright
Other

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