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Fast, Massively Parallel Data ProcessorsProposed fast, massively parallel data processor contains 8x16 array of processing elements with efficient interconnection scheme and options for flexible local control. Processing elements communicate with each other on "X" interconnection grid with external memory via high-capacity input/output bus. This approach to conditional operation nearly doubles speed of various arithmetic operations.
Document ID
19940000414
Acquisition Source
Legacy CDMS
Document Type
Other - NASA Tech Brief
Authors
Heaton, Robert A.
(Microelectronics Center of North Carolina)
Blevins, Donald W.
(Microelectronics Center of North Carolina)
Davis, ED
(North Carolina State Univ.)
Date Acquired
August 16, 2013
Publication Date
August 1, 1994
Publication Information
Publication: NASA Tech Briefs
Volume: 18
Issue: 8
ISSN: 0145-319X
Subject Category
Electronic Systems
Report/Patent Number
GSC-13304
Accession Number
94B10414
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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