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estimating delays in asic'sVerification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.
Document ID
19940000446
Document Type
Other - NASA Tech Brief
Authors
Burke, Gary
(Caltech)
Nesheiwat, Jeffrey
(Caltech)
Su, Ling
(Caltech)
Date Acquired
August 16, 2013
Publication Date
August 1, 1994
Publication Information
Publication: NASA Tech Briefs
Volume: 18
Issue: 8
ISSN: 0145-319X
Subject Category
ELECTRONIC COMPONENTS AND CIRCUITS
Report/Patent Number
NPO-19025
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.