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VLSI chip-set for data compression using the Rice algorithmA full custom VLSI implementation of a data compression encoder and decoder which implements the lossless Rice data compression algorithm is discussed in this paper. The encoder and decoder reside on single chips. The data rates are to be 5 and 10 Mega-samples-per-second for the decoder and encoder respectively.
Document ID
19940004324
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Venbrux, J. (Idaho Univ. Moscow, ID, United States)
Liu, N. (Idaho Univ. Moscow, ID, United States)
Date Acquired
August 16, 2013
Publication Date
January 24, 1990
Publication Information
Publication: The First NASA Symposium on VLSI Design
Subject Category
Electronics And Electrical Engineering
Accession Number
94N71079
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.

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IDRelationTitle19940004319Collected WorksNASA SERC 1990 Symposium on VLSI Design
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