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The application of compiler-assisted multiple instruction retry to VLIW architecturesVery Long Instruction Word (VLIW) architectures enhance performance by exploiting fine-grained instruction level parallelism. We describe the development of two compiler assisted multiple instruction word retry schemes for VLIW architectures. The first scheme utilizes the compiler techniques previously developed for processors with single functional units. A compiler generated hazard-free code with different degrees of rollback capability for uniprocessors is compacted by a modified VLIW trace scheduling algorithm. Nops are then inserted in the scheduled code words to resolve data hazards for VLIW architectures. Performance is compared under three parameters: the rollback distance for uni-processors; the number of functional units; and the rollback distance for VLIW architectures. The second scheme employs a hardware read buffer to resolve frequently occurring data hazards, and utilizes the compiler to resolve the remaining hazards. Performance results are shown for six benchmark programs.
Document ID
19940034723
Acquisition Source
Legacy CDMS
Document Type
Conference Paper
Authors
Chen, Shyh-Kwei
(NASA Langley Research Center Hampton, VA, United States)
Fuchs, W. K.
(NASA Langley Research Center Hampton, VA, United States)
Hwu, Wen-Mei W.
(Illinois Univ. Urbana, United States)
Date Acquired
August 16, 2013
Publication Date
January 1, 1994
Subject Category
Computer Programming And Software
Meeting Information
Meeting: International Federation for Information Processing, Working Conference on Dependable Computing for Critical Applications
Location: San Diego, CA
Country: United States
Start Date: January 4, 1994
End Date: January 6, 1994
Accession Number
94A11378
Funding Number(s)
CONTRACT_GRANT: NAG1-613
CONTRACT_GRANT: N00014-91-J-1283
Distribution Limits
Public
Copyright
Other

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