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Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InPMetal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.
Document ID
Document Type
Reprint (Version printed in journal)
External Source(s)
Tabory, Charles N. (Toledo Univ. OH United States)
Young, Paul G. (Toledo Univ. OH United States)
Smith, Edwyn D. (Toledo Univ. OH United States)
Alterovitz, Samuel A. (NASA Lewis Research Center Cleveland, OH United States)
Date Acquired
August 17, 2013
Publication Date
February 1, 1994
Publication Information
Publication: Journal of Vacuum Science Technology B
Volume: 12
Issue: 1
ISSN: 0734-211X
Subject Category
Solid-State Physics
Report/Patent Number
NAS 1.15:112737
Distribution Limits
Public Use Permitted.
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