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Record Details

Record 20 of 8312
2D Quantum Mechanical Study of Nanoscale MOSFETs
Author and Affiliation:
Svizhenko, Alexei(NASA Ames Research Center, Moffett Field, CA United States)
Anantram, M. P.(Computer Sciences Corp., United States)
Govindan, T. R.(NASA Ames Research Center, Moffett Field, CA United States)
Biegel, B.(Computer Sciences Corp., United States)
Kwak, Dochan [Technical Monitor]
Abstract: With the onset of quantum confinement in the inversion layer in nanoscale MOSFETs, behavior of the resonant level inevitably determines all device characteristics. While most classical device simulators take quantization into account in some simplified manner, the important details of electrostatics are missing. Our work addresses this shortcoming and provides: (a) a framework to quantitatively explore device physics issues such as the source-drain and gate leakage currents, DIBL, and threshold voltage shift due to quantization, and b) a means of benchmarking quantum corrections to semiclassical models (such as density-gradient and quantum-corrected MEDICI). We have developed physical approximations and computer code capable of realistically simulating 2-D nanoscale transistors, using the non-equilibrium Green's function (NEGF) method. This is the most accurate full quantum model yet applied to 2-D device simulation. Open boundary conditions and oxide tunneling are treated on an equal footing. Electrons in the ellipsoids of the conduction band are treated within the anisotropic effective mass approximation. We present the results of our simulations of MIT 25, 50 and 90 nm "well-tempered" MOSFETs and compare them to those of classical and quantum corrected models. The important feature of quantum model is smaller slope of Id-Vg curve and consequently higher threshold voltage. Surprisingly, the self-consistent potential profile shows lower injection barrier in the channel in quantum case. These results are qualitatively consistent with ID Schroedinger-Poisson calculations. The effect of gate length on gate-oxide leakage and subthreshold current has been studied. The shorter gate length device has an order of magnitude smaller current at zero gate bias than the longer gate length device without a significant trade-off in on-current. This should be a device design consideration.
Publication Date: Jan 01, 2000
Document ID:
20010114471
(Acquired Dec 07, 2001)
Subject Category: ELECTRONICS AND ELECTRICAL ENGINEERING
Document Type: Preprint
Meeting Information: 2nd Workshop on Computational Materials and Electronics; 9-10 Nov. 2000; Tempe, AZ; United States
Contract/Grant/Task Num: NCC2-5304; RTOP 519-40-12
Financial Sponsor: NASA Ames Research Center; Moffett Field, CA United States
Organization Source: NASA Ames Research Center; Moffett Field, CA United States
Description: 1p; In English
Distribution Limits: Unclassified; Publicly available; Unlimited
Rights: No Copyright
NASA Terms: FIELD EFFECT TRANSISTORS; METAL OXIDE SEMICONDUCTORS; CONFINEMENT; COMPUTER PROGRAMS; SIMULATION; TRANSISTORS; THRESHOLD VOLTAGE; BOUNDARY CONDITIONS; ANISOTROPY; CONDUCTION BANDS; ELECTROSTATICS
Availability Source: Other Sources
Availability Notes: Abstract Only
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