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memory-intensive benchmarks: iram vs. cache-based machinesThe increasing gap between processor and memory performance has lead to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory access patterns, their basic control structures, and the ratio of computation to memory operation.
Document ID
20020073866
Document Type
Preprint (Draft being sent to journal)
Authors
Biswas, Rupak
(NASA Ames Research Center Moffett Field, CA United States)
Gaeke, Brian R.
(California Univ. Berkeley, CA United States)
Husbands, Parry
(National Energy Research Supercomputer Center Livermore, CA United States)
Li, Xiaoye S.
(National Energy Research Supercomputer Center Livermore, CA United States)
Oliker, Leonid
(National Energy Research Supercomputer Center Livermore, CA United States)
Yelick, Katherine A.
(California Univ. Berkeley, CA United States)
Biegel, Bryan
Date Acquired
August 20, 2013
Publication Date
January 1, 2002
Subject Category
Computer Operations and Hardware
Meeting Information
IPDPS Conference(Fort Lauderdale, FL)
Funding Number(s)
PROJECT: RTOP 725-10-31
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
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