Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.