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Room and Low Temperature Performance of High-Speed Neural Network CircuitsWe have described a challenging neural-network hardware implementation that would mate a 64x64-pixel infrared sensor directly on to a 3-dimensionally packaged set of neural processing chips with parallel input for high speed image processing. Non linearity effects and range compression are also discussed.
Document ID
20060035034
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
Authors
Daud, T.
Date Acquired
August 23, 2013
Publication Date
May 3, 1997
Subject Category
Cybernetics, Artificial Intelligence And Robotics
Distribution Limits
Public
Copyright
Other
Keywords
high-speed neural network circuits neural network circuits network chips
digital-analog

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