NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Collections About News Help Login
Back to Results
(abstract) Case Study of the Design of a Viterbi DecoderThis paper describes the design of an ASIC performing the Viterbi decoder function with a constraint length of 15 and at a speed of 4.4 Mb/s. The architecture of the chip is described, as well as the design challenges which were overcome. The author also describes the successful application of the design system.
Document ID
20060036658
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
hdl:2014/27504
Authors
Burke, Gary R.
Date Acquired
August 23, 2013
Publication Date
January 21, 1997
Distribution Limits
Public
Copyright
Other
Keywords
Viterbi decoders ASIC chip architecture constraint length

Available Downloads

There are no available downloads for this record.

Related Records

There are no records associated with this record.
No Preview Available