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Digital Filter ASIC for NASA Deep Space Radio ScienceThis paper is about the implementation of an 80 MHz, 16-bit, multi-stage digital filter to decimate by 1600, providing a 50 kHz output with bandpass ripple of less than +/-0.1 dB. The chip uses two decimation by five units and six decimations by two executed by a single decimation by two units. The six decimations by two consist of six halfband filters, five having 30-taps and one having 51-taps. Use of a 16x16 register file for the digital delay lines enables implementation in the Vitesse 350K gate array.
Document ID
20060036925
Acquisition Source
Jet Propulsion Laboratory
Document Type
Preprint (Draft being sent to journal)
External Source(s)
Authors
Kowalski, James E.
Date Acquired
August 23, 2013
Publication Date
March 1, 1995
Distribution Limits
Public
Copyright
Other
Keywords
Digital Filter

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