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Impact of CMOS Scaling on Single-Event Hard Errors in Space SystemsApplications of highly scaled devices in space applications are shown to be limited by hard errors from cosmic rays. Hard errors were first observed in 0.8 (micro)m DRAMs. For feature sizes below 0.5 (micro)m, scaling theory predicts that low power devices will have much lower hard error rates than devices optimized for high speed.
Document ID
20060041863
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Johnston, A. H.
Swift, G. M.
Shaw, D. C.
Date Acquired
August 23, 2013
Publication Date
October 1, 1995
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: IEEE Symposium on Low Power Electronics
Location: San Jose, CA
Country: United States
Start Date: October 9, 1995
End Date: October 11, 1995
Distribution Limits
Public
Copyright
Other
Keywords
CMOS Scaling

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