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A novel four-quadrant analog multiplier using SOI four-gate transitors (G4-FETs)A novel analog muliplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers.
Document ID
20060042912
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Akarvardar, K.
Chen, S.
Blalock, B. J.
Cristoloveanu, S.
Gentil, P.
Mojarradi, M.
Date Acquired
August 23, 2013
Publication Date
September 1, 2005
Meeting Information
Meeting: European Solid-State Circuits Conference (ESSCIRC)
Location: Grenoble
Country: France
Start Date: September 12, 2005
End Date: September 16, 2005
Distribution Limits
Public
Copyright
Other
Keywords
SOI CMOS
analog multiplier

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