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On board processor development for NASA's spaceborne imaging radar with system-on-chip technologyThis paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with system-on-chip technology. Finally, a minimum version of this on-board processor designed for performance evaluation and for partial demonstration is illustrated.
Document ID
20060043059
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
hdl:2014/38080
Authors
Fang, Wai-Chi
Date Acquired
August 23, 2013
Publication Date
May 1, 2004
Subject Category
Communications And Radar
Meeting Information
Meeting: 2004 IEEE International Symposium on Circuits and Systems
Location: Vancouver, British Columbia
Country: Canada
Start Date: May 23, 2004
Distribution Limits
Public
Copyright
Other
Keywords
radar
system-on-chip
VLSI

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