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Onboard FPGA-based SAR processing for future spaceborne systemsWe present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.
Document ID
20060043109
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Le, Charles
Chan, Samuel
Cheng, Frank
Fang, Winston
Fischman, Mark
Hensley, Scott
Johnson, Robert
Jourdan, Michael
Marina, Miguel
Parham, Bruce
Rogez, Francois
Rosen, Paul
Shah, Biren
Taft, Stephanie
Date Acquired
August 23, 2013
Publication Date
April 1, 2004
Subject Category
Communications And Radar
Meeting Information
Meeting: IEEE 2004 Radar Conference
Location: Philadelphia, PA
Country: United States
Start Date: April 26, 2004
Distribution Limits
Public
Copyright
Other
Keywords
spaceborne systems
doppler
SAR processing
algorithm

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