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IBM powerPC 405 SEU mitigation using processor voting techniques in Xilinx Virtex-I1 pro FPGANot until recently, Xilinx has developed a new field programmable gate array (FPGA) device family, Virtex-I1 Pro. In this single device, not only dies it have density logic cells (3K to125K), gigabit connectivity, on chip memory, digital clock management, but also it can have up to four IBM PowerPC 405 Processor hard cores, running up to 400MHz and 633 Mbps. To utilize this cutting edge device in space applications, a few Single Event Upset (SEU) mitigation techniques need to be implemented to a design for the device. At Jet Propulsion Laboratory (JPL), we have successfully demonstrated the feasibility of running multiple processors running in a lock step fashion to accomplish SEU mitigation and fault tolerance.
Document ID
20060043582
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Wang, Mandy W.
Bolotin, Gary S.
Date Acquired
August 23, 2013
Publication Date
September 8, 2004
Meeting Information
Meeting: MAPLD International Conference
Location: Washington, DC
Country: United States
Start Date: September 8, 2004
End Date: September 10, 2004
Distribution Limits
Public
Copyright
Other
Keywords
single event upset (SEU)
PowerPC 405

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