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Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC MicroprocessorsSingle-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.
Document ID
20060051522
Document Type
Preprint (Draft being sent to journal)
External Source(s)
Authors
Irom, Farokh (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Farmanesh, Farhad (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Kouba, Coy K. (NASA Johnson Space Center Houston, TX, United States)
Date Acquired
August 23, 2013
Publication Date
January 1, 2006
Subject Category
Electronics and Electrical Engineering
Meeting Information
43rd Annual International Nuclear and Space Radiation Effects Conference (NSREC)(Jacksonville, FL)
Distribution Limits
Public
Copyright
Other
Keywords
silicon on insulator
Cyclotron
scaling trends
single-event upsets
heavy ion
microprocessors