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A Scalable Architecture of a Structured LDPC DecoderWe present a scalable decoding architecture for a certain class of structured LDPC codes. The codes are designed using a small (n,r) protograph that is replicated Z times to produce a decoding graph for a (Z x n, Z x r) code. Using this architecture, we have implemented a decoder for a (4096,2048) LDPC code on a Xilinx Virtex-II 2000 FPGA, and achieved decoding speeds of 31 Mbps with 10 fixed iterations. The implemented message-passing algorithm uses an optimized 3-bit non-uniform quantizer that operates with 0.2dB implementation loss relative to a floating point decoder.
Document ID
20070034969
Document Type
Preprint (Draft being sent to journal)
External Source(s)
Authors
Lee, Jason Kwok-San (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Lee, Benjamin
Thorpe, Jeremy
Andrews, Kenneth
Dolinar, Sam
Hamkins, Jon
Date Acquired
August 24, 2013
Publication Date
June 1, 2004
Subject Category
Mathematical and Computer Sciences (General)
Meeting Information
The Institute of Electrical and Electronics Engineers (IEEE)International Symposium on Information Theory(Chicago, IL)
Distribution Limits
Public
Copyright
Other
Keywords
optical communications
channel capacity
modulation