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Chip connectivity verification programA method for testing electrical connectivity between conductive structures on a chip that is preferably layered with conductive and nonconductive layers. The method includes determining the layer on which each structure is located and defining the perimeter of each structure. Conductive layer connections between each of the layers are determined, and, for each structure, the points of intersection between the perimeter of that structure and the perimeter of each other structure on the chip are also determined. Finally, electrical connections between the structures are determined using the points of intersection and the conductive layer connections.
Document ID
20080004490
Acquisition Source
Headquarters
Document Type
Other - Patent
Authors
Riley, Josh
Patterson, George
Date Acquired
August 24, 2013
Publication Date
September 7, 1999
Subject Category
Computer Operations And Hardware
Report/Patent Number
Patent Application Number: US-PATENT-APPL-SN-707649
Patent Number: US-PATENT-5,949,986
Distribution Limits
Public
Copyright
Work of the US Gov. Public Use Permitted.
Patent
US-PATENT-5,949,986
Patent Application
US-PATENT-APPL-SN-707649
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