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Testing and Qualifying Linear Integrated Circuits for Radiation Degradation in SpaceThis paper discusses mechanisms and circuit-related factors that affect the degradation of linear integrated circuits from radiation in space. For some circuits there is sufficient degradation to affect performance at total dose levels below 4 krad(Si) because the circuit design techniques require higher gain for the pnp transistors that are the most sensitive to radiation. Qualification methods are recommended that include displacement damage as well as ionization damage.
Document ID
20090014096
Document Type
Conference Paper
External Source(s)
Authors
Johnston, Allan H.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Rax, Bernard G.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 24, 2013
Publication Date
August 4, 2006
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: RADECS 2005, the 8th European Conference on Radiation and Its Effects on Components and Systems
Location: Cap d''Agde
Country: France
Start Date: September 19, 2005
End Date: September 23, 2005
Sponsors: Institute of Electrical and Electronics Engineers
Distribution Limits
Public
Copyright
Other
Keywords
integrated circuit testing
radiation effects
analogue integrated circuits
transistors
integrated circuit design

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