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Re-Configurable Electronics Characterization under Extreme Thermal EnvironmentThe need for reconfigurable electronics is driven by requirements to survive longer missions and harsher environments. It is possible to compensate for degradations in Extreme Environments (EE). EE has effect on electronics: circuits are designed to exploit device characteristics and when a certain temperature or radiation range is exceeded the circuit function gradually degrades. It is possible to employ Hardening by reconfiguration (HBR) to mitigate drifts, degradation, or damage on electronic devices in EE by using reconfigurable devices and an adaptive self-reconfiguration of circuit topology. In this manner degraded components can be salvaged, and completely damaged components can be bypassed. The challenge of conventional design is replaced with that of designing a recover process that automatically performs the (re) design in place of the designer. The objective of testing a Digital Signal Processor (DSP) under the extreme temperatures was to determine the lowest temperature at which the DAP can operate. The objective of testing a Xilinx VirtexII Pro FPGA board was to initially find our whether the evaluation board and the FPGA would survive and continue at temperature ranges from -180 C, and 120 C. The Virtex II functioned correctly at the temperatures tested. The next test was done on the GM-C filter building block using the same temperature range as the Virtex II. The current lower and upper limits were shown to be reduced as the temperature gets lower. The device function can be recovered by increasing the Vb from .08V to .85V. The negative and positive saturation voltages increases as the temperature gets higher. The function of the device can be recovered by decreasing the Vb from .8V to around .75V. The next test was performed to test the recovery of the GmC low pass filter through Vb in a filter circuit. The test indicate that bias voltage control adjustment is an efficient mechanism for circuit recovery at extreme temperatures.
Document ID
20090014179
Acquisition Source
Jet Propulsion Laboratory
Document Type
Presentation
External Source(s)
Authors
Stoica, Adrian
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Lacayo, Veronica
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Ramesham, Rajeshuni
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Keymeulen, Didier
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Zebulum, Ricardo
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Neff, Joe
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Burke, Gary
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Daud, Taher
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 24, 2013
Publication Date
September 7, 2005
Subject Category
Electronics And Electrical Engineering
Meeting Information
Meeting: Military and Aerospace Programmable Logic Devices (MAPLD) International Conference
Location: San Diego, CA
Country: United States
Start Date: September 7, 2005
End Date: September 9, 2005
Distribution Limits
Public
Copyright
Other
Keywords
reliability
Digital Signal Processor (DSP)
extreme environments
reconfigurable
FPGA

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