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Mitigating Upsets in SRAM Based FPGAs from the Xilinix Virtex 2 FamilyThis slide presentation reviews the single event upset static testing of the Virtex II field programmable gate arrays (FPGA) that were tested in protons and heavy-ions. The test designs and static and dynamic test results are reviewed.
Document ID
20090023165
Acquisition Source
Jet Propulsion Laboratory
Document Type
Presentation
External Source(s)
hdl:2014/41193
Authors
Swift, Gary M. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Yui, Candice C. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Carmichael, Carl (Xilinx Corp. San Jose, CA, United States)
Koga, Rocky (Aerospace Corp. Los Angeles, CA, United States)
George, Jeffrey S. (Aerospace Corp. Los Angeles, CA, United States)
Date Acquired
August 24, 2013
Publication Date
September 9, 2003
Subject Category
Solid-State Physics
Report/Patent Number
MAPLD Paper #P69
Distribution Limits
Public
Copyright
Other
Keywords
Single Event Effect (SEE) testing
Xilinx
FPGA

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