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FPGA Implementation of Stereo Disparity with High Throughput for Mobility ApplicationsHigh speed stereo vision can allow unmanned robotic systems to navigate safely in unstructured terrain, but the computational cost can exceed the capacity of typical embedded CPUs. In this paper, we describe an end-to-end stereo computation co-processing system optimized for fast throughput that has been implemented on a single Virtex 4 LX160 FPGA. This system is capable of operating on images from a 1024 x 768 3CCD (true RGB) camera pair at 15 Hz. Data enters the FPGA directly from the cameras via Camera Link and is rectified, pre-filtered and converted into a disparity image all within the FPGA, incurring no CPU load. Once complete, a rectified image and the final disparity image are read out over the PCI bus, for a bandwidth cost of 68 MB/sec. Within the FPGA there are 4 distinct algorithms: Camera Link capture, Bilinear rectification, Bilateral subtraction pre-filtering and the Sum of Absolute Difference (SAD) disparity. Each module will be described in brief along with the data flow and control logic for the system. The system has been successfully fielded upon the Carnegie Mellon University's National Robotics Engineering Center (NREC) Crusher system during extensive field trials in 2007 and 2008 and is being implemented for other surface mobility systems at JPL.
Document ID
20110015573
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Villalpando, Carlos Y.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Morfopolous, Arin
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Matthies, Larry
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Goldberg, Steven
(Indelible Systems, Inc. Northridge, CA, United States)
Date Acquired
August 25, 2013
Publication Date
March 5, 2011
Publication Information
ISBN: 978-1-4244-7351-9
Subject Category
Cybernetics, Artificial Intelligence And Robotics
Report/Patent Number
IEEEAC Paper 1162
Meeting Information
Meeting: 2011 IEEE Aerospace Conference
Location: Big Sky, MT
Country: United States
Start Date: March 5, 2011
End Date: March 12, 2011
Sponsors: Institute of Electrical and Electronics Engineers
Distribution Limits
Public
Copyright
Other
Keywords
Random access memory
Program processors
machine vision
Generators
Field-programmable Gate Array (FPGA)
stereo
Pixel

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