NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Back to Results
Energy Usage in an Embedded Space Vision Application on a Tiled ArchitectureThe need for greater autonomy in platforms such as planetary rovers is driving rapidly to codes that far overwhelm the capabilities of conventional space-qualified single core processors to run them in real-time. However, a new generation of potentially space-qualified 2D "tiled" multi-core microprocessor chips is emerging with significant performance potential. Leveraging such inherently parallel hardware for space platforms requires consideration of both time and power limitations - the latter of which is not normally done in conventional parallel computing. This paper takes one such application, Rockster, and analyzes it for energy usage when ported to a multi-core tiled chip such as may come from the Maestro program. The results demonstrate not only the criticality of memory and interconnect in the energy of real-time parallel codes, but also the effects of possible "energy-aware" changes in partitioning and algorithm design.
Document ID
20120007455
Acquisition Source
Jet Propulsion Laboratory
Document Type
Conference Paper
External Source(s)
Authors
Kogge, Peter M.
(Notre Dame Univ. IN, United States)
Bornstein, Benjamin J.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Estlin, Tara A.
(Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 25, 2013
Publication Date
March 29, 2011
Subject Category
Computer Programming And Software
Meeting Information
Meeting: AIAA Infotech@Aerospace Conference
Location: Saint Louis, MO
Country: United States
Start Date: March 29, 2011
Sponsors: American Inst. of Aeronautics and Astronautics
Distribution Limits
Public
Copyright
Other
Keywords
multi-core processors
rover autonomy

Available Downloads

There are no available downloads for this record.
No Preview Available