NASA Logo

NTRS

NTRS - NASA Technical Reports Server

Collections About News Help Login
Back to Results
Fault Mitigation Schemes for Future Spaceflight Multicore ProcessorsThe goal of this work is to achieve fail-operational and graceful-degradation behavior in realistic flight mission scenarios, of multicore processors such as Mars Entry-Descent-Landing (EDL) and Primitive Body proximity operations.
Document ID
20130010645
Acquisition Source
Jet Propulsion Laboratory
Document Type
Presentation
External Source(s)
hdl:2014/42750
Authors
Some, Rafi (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Gostelow, Kim P. (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Lai, John (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Reder, Leonard (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Alexander, James (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Clement, Brad (Jet Propulsion Lab., California Inst. of Tech. Pasadena, CA, United States)
Date Acquired
August 27, 2013
Publication Date
June 20, 2012
Subject Category
Computer Operations And Hardware
Meeting Information
Meeting: AIAA Infotech 2012
Location: Garden Grove, CA
Country: United States
Start Date: June 19, 2012
End Date: June 21, 2012
Sponsors: American Inst. of Aeronautics and Astronautics
Distribution Limits
Public
Copyright
Other
Keywords
single-core architecture
multi-core processing
Hardware fault mitigations

Available Downloads

There are no available downloads for this record.

Related Records

There are no records associated with this record.
No Preview Available